RDAH=00, AA=0, BSTW=0, PS=00, BEM=0, BSTR=0, EXTS=0, WRAH=00, SWSEN=0, ASET=00, BLS=0
Chip select control register
| BSTW | Burst-write enable 0 (0): Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. 1 (1): Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. |
| BSTR | Burst-read enable 0 (0): Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. 1 (1): Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. |
| BEM | Byte-enable mode 0 (0): The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only. 1 (1): The FB_BE n signals are asserted for read and write accesses |
| PS | Port size 0 (00): 32-bit port size. Valid data sampled and driven on FB_D[31:0] 1 (01): 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1 2 (10): 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 3 (11): 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 |
| AA | Auto-acknowledge enable 0 (0): No internal FB_TA is asserted. Cycle is terminated externally 1 (1): Internal transfer acknowledge is asserted as specified by WS |
| BLS | Byte-lane shift 0 (0): Not shifted. Data is left-justfied on FB_AD. 1 (1): Shifted. Data is right justified on FB_AD. |
| WS | Wait states |
| WRAH | Write address hold or deselect 0 (00): Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn) 1 (01): Hold address and attributes two cycles after FB_CSn negates on writes. 2 (10): Hold address and attributes three cycles after FB_CSn negates on writes. 3 (11): Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0) |
| RDAH | Read address hold or deselect 0 (00): If AA is cleared, 1 cycle. If AA is set, 0 cycles. 1 (01): If AA is cleared, 2 cycles. If AA is set, 1 cycle. 2 (10): If AA is cleared, 3 cycles. If AA is set, 2 cycles. 3 (11): If AA is cleared, 4 cycles. If AA is set, 3 cycles. |
| ASET | Address setup 0 (00): Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn) 1 (01): Assert FB_CSn on second rising clock edge after address is asserted. 2 (10): Assert FB_CSn on third rising clock edge after address is asserted. 3 (11): Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) |
| EXTS | no description available 0 (0): FB_TS /FB_ALE asserts for one bus clock cycle 1 (1): FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts |
| SWSEN | Secondary wait state enable 0 (0): The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers 1 (1): The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations |
| SWS | Secondary wait states |